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Embedded Computing |
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Digital Signal Processors |
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FPGA Processors |
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- Virtex-5 FPGA - |
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VPX - 4x V5 |
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VPX 2xV5 & 2xPowerPC |
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VPX - 2x V5 & PowerPC |
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VXS - V5 & PowerPC |
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PCI - V5 Digital IO |
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PMC - V5 Digital IO |
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XMC - V5 Analog 1.5GS |
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XMC - V5 Analog 3GS |
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- Virtex-4 FPGA - |
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VPX - V4 for DSP |
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VPX - V4 for Logic |
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VXS - V4 for DSP |
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VXS - V4 for Logic |
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VXS - V4 IO Controller |
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PMC - V4 Logic Node |
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PMC - V4 DSP Node |
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PMC - V4 Dual Logic |
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- Virtex-II Pro - |
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PMC - V2Pro Digital IO |
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VXS - V2Pro & PowerPC |
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PMC - V2Pro Fiber IO |
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3U - V2Pro & PowerPC |
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- Tools - |
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FPGA Toolkit |
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Single Board Computers |
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Switch Cards |
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Digital I/O |
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Analog I/O |
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Fiber Optic I/O |
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Carriers |
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Buffer Memory Nodes |
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Ethernet |
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Chassis |
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Software |
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IP Cores |
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Mature Products |
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Data Recording & Storage |
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Protocol & Bus Analyzers |
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Network Storage |
The PMC-FPGA03 is a Xilinx XC2PV50 Virtex-II Pro based FPGA PMC module with high-speed digital I/O.
The PMC-FPGA03 is optimized for computationally intensive applications. The module is available in commercial, air-cooled and rugged, conduction cooled variants.
Overview
The PMC-FPPGA03 provides developers with access to a powerful Virtex-II Pro platform FPGA - the performance of which is enhanced by large external memory structures, making the PMC-FPGA03 ideal for a wide range of reconfigurable computing applications. Two main features of the Virtex-II Pro FPGA are the inclusion, as hard-IP, of embedded IBM PowerPC 405 RISC CPU cores and RocketIO Multi-Gigabit Transceivers (MGTs) for high speed serial communications.
Digital I/O
138 single-ended lines, directly connected to the FPGA, are routed to the front panel with a separate bank of 64 single-ended lines routed to the PMC user I/O connector. Each bank is independently configurable to 2.5V or 3.3V signaling, and each bank can be configured for differential signaling.
As an alternative to parallel digital I/O, the PMC-FPGA03 can be supplied as a build option with high-speed serial communications via the FPGA's embedded Gbps RocketIO transceivers. These interfaces can be used as low level 'data pipes' or configured (using appropriate IP) to one of many standard serial communications protocols such as serial RapidIO, Infiniband or Gigabit Ethernet. The embedded PowerPC 405 processors are ideally suited to higher-level control functions such as running the protocol stacks for these interfaces.
Memory
Two independent banks of 16-bit, 64Mbytes DDR SDRAM are connected directly to the FPGA. Clocked at 125MHz, the banks can be used completely independently (e.g. 500Mbytes/s 'ping-pong' memory operations) or collectively as a single 32-bit wide, 1Gbytes/s memory structure. This memory is accessible from the PCI bus and provides a large pool of memory to buffer DMA transfers and other large data block operations.
Software
Nearly all of the FPGA resource is left free for user applications. To aid FPGA configuration, example VHDL library code blocks are provided to show how the PMC-FPGA03 resources can be used. Flash programming utilities are also provided.
For the PMC host, a board support package is provided with C++ libraries for controlling DMA transfers and interrupts handling.
Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.